Silicon-on-insulator (SOI) semiconductor devices generally include a silicon island formed on the surface of an insulating material. A metal-oxide-semiconductor (MOS) transistor is formed in and on the silicon island. When the insulating material is a sapphire substrate, the structure is known as a silicon-on-sapphire (SOS) semiconductor device. However, the insulating material may also be a layer of silicon dioxide which is disposed on a semiconductor substrate. MOS/SOI transistors generally have higher speed and improved radiation hardness in comparison with MOS transistors formed in bulk silicon.
Referring now to FIG. 1, a conventional silicon-on-insulator semiconductor device is generally designated as 10. The device 10 is a silicon-on-sapphire semiconductor device because a silicon island 12 is formed on a sapphire substrate 14. The silicon island 12 is doped P-type; however, it also contains N-type source and drain regions 13 and 15, respectively. A gate oxide (not shown) is disposed on the surfaces of the silicon island 12 under at least the gate electrode 20. The device 10 actually consists of three transistors in parallel. The first transistor is on the top surface 16 of the silicon island 12. Two transistors are also formed along the opposed sidewalls 18 of the silicon island 12. The opposed sidewalls 18 lie under the gate electrode 20 and extend along the channel length of the SOS device. The transistors formed along the opposed sidewalls 18 are commonly referred to as parasitic edge transistors.
The parasitic edge transistors have a lower threshold voltage than the top transistor. The parasitic edge transistors are also strongly susceptible to contamination from the underlying substrate material which causes the threshold voltage of the edge transistor to shift. This shifting threshold voltage can cause the edge transistor to turn on making the overall transistor appear to have a high leakage current. The parasitic edge transistor problem is more pronounced in N-channel devices when such devices are exposed to ionizing radiation. The ionizing radiation causes positive charges to build up in the gate oxide along the edge of the transistor. The positive charges turn on the edge transistor before the top transistor and a leakage path is created between the source and drain.
Commonly assigned U.S. Pat. No. 3,890,632 entitled "Stabilized Semiconductor Devices And Method of Making The Same" which issued to W. E. Ham et al. on June 17, 1975 describes a technique for decreasing the leakage currents associated with the edge transistors. In an N-channel device, the sloped sidewalls of the silicon island are ion implanted with boron before the gate electrode is applied. This doping step increases the threshold voltage of the channel region which is under the portion of the gate electrode which passes down the sidewall of the silicon island. By increasing the doping concentration of the channel region of the edge transistor, the threshold voltage is significantly increased and the leakage currents associated with the premature turn on of the edge transistor are reduced.
Since all of the sidewalls of the silicon island in U.S. Pat. No. 3,890,632 have an increased P-type doping concentration, the breakdown voltage between the channel region and the drain region of this device is significantly lowered. In order to overcome this problem, commonly assigned U.S. Pat. No. 4,054,895 entitled "Silicon-On-Sapphire Mesa Transistor Having Doped Edges" issued to W. E. Ham on Oct. 18, 1977 discloses a technique of raising the threshold voltage of the edge transistors by doping the channel edge regions adjacent the source region. The portions of the channel edge region adjacent the drain are not doped and this provides a higher breakdown voltage between the channel region along the sidewall and the drain.
When the channel length of the device is on the order of a few microns, it is difficult to selectively dope only a portion of the channel region as described in U.S. Pat. No. 4,054,895. Thus, a technique is needed to minimize leakage associated with the parasitic edge transistor in semiconductor devices which have short channel lengths.